Abstract: As one of the important integration technologies in the More than Moore Era, Through Silicon Via（TSV） technology is now rapidly developing and widely used in industry. 3D-TSV is the core of TSV technology, and is also the key to realize chip-scale interconnections. In this paper, through the study of 3D-TSV plating additive content, plating time, diffusion time and plating stirring speed and other processes, we have obtained the best plating process parameters, and obtained a smooth and uniform surface plating layer, to achieve the mainstream hole type 10 μm×100 μm defect-free filling, and flat and no hollow defects after the CMP（chemical mechanical polish） The surface is clean and homogeneous.